Moore's Law · VLSI Circuit Design Flow · Y-Chart · Design Styles · Physical Design Rules
Moore's Law (1965, Gordon Moore, Intel co-founder) states: "The number of transistors on a chip doubles approximately every 18–24 months while the cost per transistor halves."
📊 Transistor Count Growth (Relative Scale)
Think of your Jio 5G SIM card. The network chip inside Jio's base stations follows Moore's Law — packed with billions of transistors to handle millions of calls simultaneously. In 1990, that entire phone network would have needed a building full of equipment. Today it fits on a chip smaller than your thumbnail!
↑ Increasing Trends:
↓ Decreasing Trends:
A VLSI Design Flow is the step-by-step process used to convert a system specification into a working silicon chip. It's like a recipe — each step must be completed correctly before moving to the next.
When Qualcomm designs the Snapdragon 8 Gen 3 chip used in Samsung Galaxy phones sold across India: Engineers first write the specification (4G/5G modem + AI processor + GPU), then design in RTL using Verilog, synthesise to gates, do physical layout in Cadence Virtuoso, send the GDSII file to TSMC (fab in Taiwan), receive back silicon wafers, test each die, and package it — the entire flow takes 2–3 years!
As transistors pack closer, heat generation becomes critical. Dynamic power (switching) and static power (leakage) must be minimised. A smartphone chip consuming too much power drains battery fast.
Propagation delay through logic paths must meet timing constraints. Critical path determines maximum clock frequency. Setup and hold time violations cause functional errors.
More functions = more transistors = larger die area = higher cost. Area optimisation using smaller feature sizes allows fitting more logic without increasing cost.
Smaller transistors are more susceptible to electromigration, hot carrier effects, and oxide breakdown. Designs must be robust over 10+ year lifetimes.
Dense chips generate enormous heat (Apple M2 chip dissipates ~100W). Thermal vias, heat spreaders, and cooling systems must be co-designed with the chip.
At sub-10nm, random dopant fluctuations and line-edge roughness cause transistors on the same chip to vary significantly — requiring statistical design techniques.
When you play BGMI (Battlegrounds Mobile India) for 2 hours on your OnePlus phone, the Snapdragon chip heats up and throttles its speed. This is the power-speed-thermal triangle of VLSI design — the biggest challenge for every chip designer at companies like MediaTek (chips in most budget Indian phones).
The Y-Chart (proposed by Gajski and Kuhn, 1983) is a conceptual model that organises VLSI design into three domains arranged like the letter Y, with multiple levels of abstraction along each axis.
Describes what the system does — its function and algorithm. Levels from top:
Describes how the system is constructed from components:
Describes the geometric layout on silicon:
Key Insight: The Y-Chart shows that at every level of abstraction, all three domains must be considered together. Moving inward on the Y = going to lower abstraction (more detail). Moving outward = higher abstraction (system view). Design synthesis is moving between domains at the same level.
Every transistor, every wire is designed from scratch by hand. Designer has complete control over geometry, sizing, and placement.
Apple's M-series chips use full-custom design for their high-performance cores. Apple engineers hand-optimise the critical paths (ALU, cache) in Cadence Virtuoso, spending months to shave a few picoseconds off the delay. That's why Apple chips outperform competitors with the same transistor count.
Uses pre-designed, pre-characterised cells from a library. Designer connects them according to the netlist — no need to design individual transistors.
Standard Cell Design
Gate Array / FPGA
| Parameter | Full Custom | Standard Cell | FPGA |
|---|---|---|---|
| Design Time | Very Long | Medium | Short |
| Performance | Best | Good | Moderate |
| Area Efficiency | Best | Good | Poor (2–5× overhead) |
| NRE Cost | Very High | High | Low |
| Flexibility | None | Low | High |
| Volume Usage | High volume | Medium-High | Low–Medium |
ISRO's Chandrayaan-3 mission used radiation-hardened FPGAs (from Xilinx/AMD) for onboard processing — because they're reprogrammable even after launch. The Ground Control at ISTRAC Bengaluru sends updated programs to reconfigure the FPGA mid-mission. That's the power of semi-custom design!
Design Rules are geometric constraints that define minimum dimensions and spacings for layout patterns to ensure correct fabrication. They are specified by the fab (foundry) and must be strictly followed.
Rules are expressed in lambda (λ) units where λ = half the minimum feature size, OR in actual microns/nanometers.
A Stick Diagram is a simplified, schematic representation of a CMOS layout using colour-coded lines. It shows the topology (connectivity) without exact dimensions — a bridge between schematic and mask layout.
Standard Colour Coding:
Steps to draw Stick Diagram:
A stick diagram is like the sketch on a napkin an architect draws before creating detailed CAD drawings. When building a Metro station in Pune, the architect first sketches which rooms connect where (stick diagram), then creates exact blueprints with measurements (layout). Similarly, a chip designer sketches the stick diagram to plan connectivity, then converts to exact layout with λ-rule dimensions.
Layout is the actual mask-level representation of the circuit — polygons on different layers that define the physical structure of the chip. Tools like Cadence Virtuoso, Mentor Graphics Calibre are used.
| Layer | Purpose | Colour (typical) |
|---|---|---|
| N-Well | PMOS substrate region | Light green |
| Active (OD) | Transistor source/drain/channel | Yellow-green |
| Polysilicon (PO) | Gate electrode | Red |
| Contact (CO) | Active/Poly to Metal 1 | Black square |
| Metal 1 (M1) | First routing layer | Blue |
| Via (V1) | Metal 1 to Metal 2 | Black square |
| Metal 2 (M2) | Second routing layer | Pink/Magenta |
Euler's method is used to find the optimal gate ordering in a standard cell layout to minimise the number of diffusion breaks (which wastes area). The steps are:
Why Euler's Rule Matters: Diffusion breaks (where n-diffusion is interrupted) waste silicon area. Using Euler's path, designers can eliminate breaks and reduce cell area by 20–30%. Intel uses this technique in every standard cell library design at their fabs.
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