Unit 1 · System Design using Verilog | Dept. of Electronics Engineering (VLSI D&T)
Design circuits by connecting gates and modules, just like assembling a smartphone motherboard.
Describe what a circuit does, not how it's built — like writing an app in code.
Test your design virtually before burning it to actual silicon or an FPGA chip.
Truth tables, test methodology, propagation delay — ensure correctness before fabrication.
Logic with memory — flip-flops, latches, state machines (like OTP logic on your phone).
The building blocks of Verilog — ports, data-flow, gate types, operators, operands.
An HDL is a programming language used to model electronic systems. Unlike C or Python that run on CPUs, HDL code describes the actual hardware that you want to synthesise (build) on a chip or FPGA.
Think of Verilog like a house blueprint (naksha). When you ask an architect to build a 3BHK flat in Mumbai, you give them a blueprint — it describes every room, wire, and pipe. The builder (synthesis tool) then constructs the actual flat (chip). Verilog is that blueprint for digital circuits!
Verilog is the industry-standard HDL. It is used by companies like Intel, NVIDIA, Qualcomm (makers of chips in your Jio 5G phone) to design billions of logic gates. It has a C-like syntax, making it accessible for engineering students.
Did you know? The Snapdragon processor inside most Indian flagship smartphones (OnePlus, Redmi, Realme) was designed using Verilog HDL before being manufactured in TSMC's fab in Taiwan!
Describes the circuit using primitive gates: and, or, not, nand, nor, xor. Like building a LEGO model piece by piece.
Describes how data flows using assign statements and expressions. Like writing the formula for a calculation.
Describes circuit behaviour using always blocks and procedural statements. Closest to software programming.
Describes circuits at the MOSFET transistor level — the most detailed, rarely used in typical design.
Structural modelling involves connecting basic logic gates like a circuit diagram. You instantiate gates and connect them using nets (wires).
Imagine a UPI payment: the transaction succeeds only if your balance is sufficient AND the internet is available AND the receiver's UPI ID is valid. This is a 3-input AND gate!
// UPI Success = Balance_OK AND Internet_OK AND UPI_ID_Valid
and upi_gate(success, balance_ok, internet_ok, upi_valid);
module and_gate ( input A, B, output Y ); and g1 (Y, A, B); // primitive gate instantiation endmodule
module half_adder ( input A, B, output Sum, Carry ); xor g1 (Sum, A, B); // Sum = A XOR B and g2 (Carry, A, B); // Carry = A AND B endmodule
Verifying the half adder — adding two single bits (like 1-bit processor flags):
| A | B | Sum (A⊕B) | Carry (A·B) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
In real hardware, gates are NOT instant. Signal takes time to pass through a gate — called propagation delay. In Verilog, we model this using #delay.
When you send a WhatsApp message, it takes a small time to reach the server and then the recipient. Similarly, a signal through a NAND gate has a 2ns delay in real chips.
// Gate with propagation delay of 2 time units
and #2 g1 (Y, A, B); // output Y appears 2 units after A,B change
Describes circuits using Boolean expressions with the assign keyword. This models how data flows through the circuit continuously.
module half_adder_df ( input A, B, output Sum, Carry ); assign Sum = A ^ B; // XOR → bitwise exclusive-or assign Carry = A & B; // AND → bitwise and endmodule
Uses always blocks with procedural statements. Can model both combinational and sequential circuits. Sensitive list controls when the block executes.
Your Zomato app always watches (always @) the order status. Whenever it changes (Placed → Accepted → Out for Delivery → Delivered), the app updates the UI. Similarly, always @(A or B) means "run this block whenever A or B changes."
module mux4to1 ( input [3:0] D, // 4 data inputs input [1:0] SEL, // 2-bit select output reg Y ); always @(D or SEL) begin case (SEL) 2'b00: Y = D[0]; 2'b01: Y = D[1]; 2'b10: Y = D[2]; 2'b11: Y = D[3]; endcase end endmodule
A 4:1 MUX is like your Tata Sky / Airtel DTH remote: you have 4 incoming channels (inputs D0–D3), and the channel number buttons (SEL) select which one appears on your TV screen (output Y). Only one channel is displayed at a time!
Always active. Used for combinational logic. Output updates automatically whenever any input changes.
assign Y = A & B;
Executes when triggered by sensitivity list. Used for both combinational and sequential logic.
always @(posedge clk)
Sequential circuits have memory — the output depends not just on current inputs, but also on past history. They are driven by a clock signal.
When you enter your SBI ATM PIN, the machine remembers each digit you pressed (it stores state). After 4 digits, it checks the sequence. This is exactly how a sequential FSM (Finite State Machine) works — it remembers what happened before!
A D flip-flop captures the value of input D on the rising edge of the clock and holds it until the next clock edge.
module d_ff ( input D, clk, rst, output reg Q ); always @(posedge clk or posedge rst) begin if (rst) Q <= 1'b0; // synchronous reset else Q <= D; // capture D on rising clock edge end endmodule
In IRCTC tatkal booking at 10:00 AM exactly: the moment the clock "ticks" to 10:00 (rising edge), whatever the system was holding (train & class selected = D input) gets confirmed into your booking (Q output) and held until you cancel. That's a D flip-flop!
| clk (edge) | rst | D | Q (next) |
|---|---|---|---|
| ↑ Rising | 1 | X | 0 (Reset) |
| ↑ Rising | 0 | 0 | 0 |
| ↑ Rising | 0 | 1 | 1 |
| No edge | X | X | Q (hold) |
A module is the fundamental building block of Verilog. Every design starts with module and ends with endmodule. Ports define the interface (inputs/outputs).
module module_name (port_list); // declaration // 1. Port declarations input wire A, B; // input ports output wire Y; // output port inout wire Z; // bidirectional (e.g. I2C bus) // 2. Internal signals wire temp; // internal net reg count; // register (holds value) // 3. Logic (structural / data-flow / behavioural) assign Y = A & B; endmodule
Your Redmi smartphone is a module:
• Inputs: touchscreen, mic, camera, USB-C charger
• Outputs: speaker, display, vibration motor
• Internal registers: RAM, storage (holds data)
• Logic: the processor running MIUI (the always block!)
A module can be used inside another module — called instantiation. Like reusing a standard LEGO block in multiple builds.
module full_adder ( input A, B, Cin, output Sum, Cout ); wire s1, c1, c2; // Instantiate half adder modules half_adder HA1 (.A(A), .B(B), .Sum(s1), .Carry(c1)); half_adder HA2 (.A(s1), .B(Cin), .Sum(Sum),.Carry(c2)); or g1 (Cout, c1, c2); endmodule
| Type | Use | Example |
|---|---|---|
wire | Nets/connections | wire Y; |
reg | Holds value in always | reg Q; |
integer | Integer loops | integer i; |
parameter | Constants | parameter N=8; |
Format: size'base value
| Example | Meaning |
|---|---|
4'b1010 | 4-bit binary 10 |
8'hFF | 8-bit hex 255 |
8'd200 | 8-bit decimal 200 |
1'b0 | 1-bit binary 0 |
| Category | Operators | Example | Result |
|---|---|---|---|
| Bitwise | & | ^ ~ ^~ | 4'b1010 & 4'b1100 | 4'b1000 |
| Logical | && || ! | 1 && 0 | 0 |
| Reduction | &A |A ^A | &4'b1111 | 1 |
| Relational | == != > < >= <= | A == B | 1 or 0 |
| Shift | << >> | 4'b0001 << 2 | 4'b0100 |
| Arithmetic | + - * / % | 3 + 5 | 8 |
| Conditional | ? : | SEL ? A : B | A if SEL=1 |
| Concatenation | { } | {A,B} A=1,B=0 | 2'b10 |
• Conditional operator: Your phone shows "Low Battery" warning — battery < 20 ? red_icon : green_icon
• Shift left (<<): Doubling a value is like switching from 4G to 5G — double the speed, same data.
• Concatenation {}: Like merging two Jio SIM contacts lists into one phone book.
Click an option to answer. Instant feedback with explanations!
Keep practicing — you've got this! 💪
Click on any question to reveal the answer. Ideal for 2–3 mark questions.
Click to expand. These cover 5–10 mark university questions.